Determining the loop noise bandwidth and the coherent integration time is essential and
important for the design of a reliable digital phase-locked loop (DPLL) in global navigation satellite
system (GNSS) receivers. In general, designers set such parameters approximately by utilizing
the well-known fact that the DPLL is stable if the normalized bandwidth, which is the product
of the integration time and the noise bandwidth, is much less than one. However, actual limit
points are not fixed at exactly one, and they vary with the loop filter order and implementation
method. Furthermore, a lower limit on the normalized bandwidth may exist. This paper presents
theoretical upper and lower limits for the normalized bandwidth of DPLL in GNSS receivers. The
upper limit was obtained by examining the stability of DPLL with a special emphasis on the digital
integration methods. The stability was investigated in terms of z-plane root loci with and without
the consideration of the computational delay, which is a delay induced by the calculation of the
discriminator and the loop filter. The lower limit was analyzed using the DPLL measurement error
composed of the thermal noise, oscillator phase noise, and dynamic stress error. By utilizing the
carrier-to-noise density ratio threshold which indicates the crossing point between the measurement
error and the corresponding threshold, the lower limit of the normalized bandwidth is obtained.
«Determining the loop noise bandwidth and the coherent integration time is essential and
important for the design of a reliable digital phase-locked loop (DPLL) in global navigation satellite
system (GNSS) receivers. In general, designers set such parameters approximately by utilizing
the well-known fact that the DPLL is stable if the normalized bandwidth, which is the product
of the integration time and the noise bandwidth, is much less than one. However, actual limit
points are not fi...
»