This work describes simulation, fabrication and characterization of junction field effect transistors, JFETs, following a concept not previously realized on silicon substrate. This new concept consists in dividing the channel of the JFETs into two regions: a main channel and an extended drain channel. This concept allows DC characteristics, such as channel current and transconductance, to be set largely independent of the length of the top gate control electrode. In the first chapter, all relevant theoretical fundamentals of dc current and noise characteristics of JFETs are reviewed. Special emphasis is placed here on the thermal noise of short-channel JFETs. In the next chapter, feasibility and expected parameters are evaluated by simulating the fabrication process as well as electrical simulation of the resulting device. To increase the prediction probability of the simulator, simulation parameters were adjusted to measurement results from preceding tests. The new values obtained are compared with measurement results. The realization is carried out within the framework of a technology platform, which is based on a CMOS manufacturing process. An overview of the basic manufacturing process is given and structure variants are explained. The characterization includes DC parameters such as channel current, transconductance, output resistance and input current. AC current parameters measured are capacitances of top and bottom gate to channel, and frequency-dependent and frequency-independent noise. For white noise characterization, a comparison is made with simulated values and the discrepancy between simulation, measurement and established models from publications is discussed. Finally, applications realized with partners during the work on the topic are presented and the obtained results are compared with the state of the art as well as an outlook on the topic is given.