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Document type:
Konferenzbeitrag / Conference Paper
Title:
How to build a Generic Model of complete ICs for system ESD and electrical stress simulation?
Title of conference publication:
2017 39th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)
Subtitle of conference publication:
10-14 Sept. 2017
Conference title:
Electrical Overstress/Electrostatic Discharge Symposium (39., 2017, Tucson, AZ)
Venue:
Tucson, AZ, USA
Year of conference:
2017
Date of conference beginning:
10.09.2017
Date of conference ending:
14.09.2017
Publisher:
IEEE
Year:
2017
Pages from - to:
1-10
Language:
Englisch
Abstract:
For precise system ESD simulation the transient chip behavior needs to be modeled accurately. As there are several typical characteristics possible (e.g. diode breakdown, snapback-element or forward diode) a straight forward methodology to build a generic model for transient behavior with destruction limits in SPICE is presented. This enables full-system transient ESD and electrical stress simulation for system robustness evaluation.
ISBN:
978-1-58537-293-5
Department:
Fakultät für Elektrotechnik und Informationstechnik; Fakultät für Elektrotechnik und Technische Informatik
Institute:
EIT 4 - Institut für Mikroelektronik und Schaltungstechnik; ETTI 1 - Institut für Physik, Elektrotechnik und Automatisierungstechnik
Chair:
Maurer, Linus; Sauter, Martin
Open Access yes or no?:
Ja / Yes
BibTeX